1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly relates to a semiconductor device including a calibration circuit for adjusting an output impedance of an output buffer circuit.
2. Description of Related Art
In recent years, a data transfer between semiconductor devices (such as between a CPU and a memory device) requires a very high data-transfer rate. To achieve this, an amplitude of an input/output signal is made increasingly smaller. When an input/output signal has a small amplitude, the required precision of an impedance of an output buffer circuit becomes very severe.
The impedance of an output buffer circuit not only fluctuates according to a processing condition at a time of manufacturing but also is influenced by an ambient temperature and a fluctuation of a power source voltage when the output buffer circuit is actually used. Therefore, when the output buffer circuit is required to have a high precision of an impedance, an output buffer circuit having an impedance adjusting function is employed. An impedance of such an output buffer circuit is generally adjusted by using an output-impedance adjusting circuit called “calibration circuit”. See Japanese Patent Application Laid-open Nos. 2002-152032, 2004-32070, 2006-203405 and 2005-159702.
As described in Japanese Patent Application Laid-open Nos. 2006-203405 and 2005-159702, a calibration circuit includes a replica buffer circuit having the same configuration as that of an output buffer circuit. When a calibration operation is performed, a potential appearing at a calibration terminal is compared with a reference potential in a state where an external resistor is connected to the calibration terminal, thereby adjusting an impedance of the replica buffer circuit. Adjustment details on the replica buffer circuit are then reflected on the output buffer circuit to adjust an impedance of the output buffer circuit to a desired value.
A calibration circuit includes a reference-potential generating circuit that generates a reference potential. Because the reference-potential generating circuit includes a plurality of resistive elements connected in series, a current continuously flows therethrough during generation of the reference potential. However, because a calibration operation using the calibration circuit is an intermittent operation which is not always performed but is performed each time a calibration command is issued, the power consumption by the reference-potential generating circuit can be reduced if the reference-potential generating circuit is also activated in response to the calibration command.
In the method of activating the reference-potential generating circuit in response to the calibration command, however, it takes a certain amount of time from when the reference-potential generating circuit is activated until when an appropriate reference potential is generated. Besides, this time varies according to chips, and in some chips, a comparison operation by a comparison circuit is started before an appropriate reference potential is generated. In such a case, the impedance of the replica buffer circuit is set to an inappropriate value.